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Wafer level packaging using StressedMetal™ technology


In earlier reports, StressedMetal™ springs have been demonstrated in dense arrays of 6-micron pitch interconnects, optoelectronic modules, and in high quality factor RF coils on BiCMOS circuits. In this report we will cover recent developments directed at utilizing the StressedMetal™ technology for wafer level packaging (WLP). What we seek to enable is a low-cost compliant interconnect that is batch fabricated onto the wafer as the last metallization step. The interconnect's z-compliance can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using an SMT compatible process. As a specific example of this concept, we fabricated daisy chain test vehicles on die measuring 11.4 mm by 6.5 mm with 48 spring contacts on a 0.8mm by 1mm grid array, each spring measuring 400 microns by 100 microns. The parts were placed onto organic boards with screen printed lead-free solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring. Assembled parts have undergone 19,500 thermal cycles from -10 °C to +150 °C at 6min/cycle, and 2400 thermal cycles from -40ºC to +125ºC at 45 min/cycle, both without failure.


Fork, D. K. ; Chua, C. L. ; Van Schuylenbergh, K. ; Chow, E. M. ; Hantschel, T. ; Kosgalwies, S. ; Wong, L. ; Geluz, V. Wafer level packaging using StressedMetal™ technology. Proceedings of the 37th International Symposium on Microelectronics (IMAPS 2004) on CDROM; 2004 November 14-17; Long Beach; CA.