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Fine-feature patterning of giant-area flexible electronics by microcontact printing and digital lithography


The development of inexpensive high-performance electronics requiring low-temperature device processing would enable low-cost, giant-area flexible electronics for applications such as high-resolution giant-area displays, sensors, and evolving technologies such as electric paper. The spatial resolution, small drop volume and large-area coverage of jet-printing methods, combined with fine feature stamping and low-temperature semiconductor processing, is one approach for integrating high-performance thin-film transistors (TFTs) with giant-area flexible substrates. A novel digital-lithographic method, in which an electronically generated and digitally aligned etch mask is jet-printed onto a process surface, was used to fabricate hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) arrays. The digital lithographically fabricated arrays had features as small as 30 m with 5 m layer-to-layer registration and pixel resolution of 75 dpi over a four-inch diameter wafer. The resulting TFTs possessed on/off ratios of 108 and threshold voltages of 2-3 V. To further demonstrate the efficacy of the digital lithographic process, the technique has been applied to fabricate a-Si based TFTs backplanes on to flexible substrates. Given the ability for high-resolution spatial alignment, the digital lithographic process is ideal for registering multilayer patterns over a large-area flexible substrate in which localized alignment run out is a problem. In combination with digital lithography, a low temperature a-Si:H based TFT deposition process (T~170°C) was used to fabricate TFT devices having threshold voltages of 4 V and on/off ratios of 108 and carrier mobility of 0.9 cm2/V•s, comparable to conventional a-Si:H TFT devices. The same process was used to make 128×128 pixel matrix addressed TFT arrays having 75 dpi resolution on polyimide and polyethylene napthalate flexible substrates. Device characteristics for the low-temperature TFT arrays on flex will be presented and compared to devices created by conventional methods. In order to achieve smaller pattered features, the digital lithography process has been combined with micro-contact printing methods in order to pattern TFT device structures with channel lengths as short as 5 microns. In this process, a poly(dimethylsiloxane) stamp was used to pattern fine feature masks within a pixel and digital lithography was used to pattern the features for the giant-area electronics. We will present various techniques for all print patterned giant-area electronics. All jet-print patterned TFT pixel designs having a minimum feature size of < 10 microns and integration of the flexible TFT array backplane with electrophoretic display media will also be discussed.


Wong, W. S. ; Chabinyc, M. ; Chow, E. M. ; Lujan, R. A. ; Daniel, J. H. ; Street, R. A. Fine-feature patterning of giant-area flexible electronics by microcontact printing and digital lithography. Proceedings of the Spring 2005 Materials Research Society Meeting; 2005 March 28 - April 1; San Francisco; CA.