ClawConnect™ Stacked Packages

The rapid proliferation of mobile applications is driving the demand for compact, high-density IC (integrated circuit) modules. PARC’s ClawConnect™ stacked package technology enables the next generation of these modules by providing low-cost assembly of thinly stacked, testable, and re-workable memory and logic ICs.

Existing stacking technologies are limited by:
-	poor testability and lack of re-workability at all stages of assembly;
-	large solder balls which limit thinness, and impede die test and burn-in;
-	increasing wire-bond complexity as stacks grow beyond 4 die;
-	thermal management of the stack’s inner layers.

PARC’s ClawConnect™ stacked package solution resolves these issues, enabling taller stack assembly with lower total cost.

Stack of 8 memory ICs less than 1.2 mm thick, enabled by ClawConnect™spring interconnects

Solution Features

• Testing and burn-in of each stacked layer prior to and after stack assembly
• Re-work of faulty die layers because the interlayer contacts are solder-free
• Thinner stacks— down to 1.2 mm for 8-DRAM (dynamic random access memory) die stacks for early generation modules
• Integrated thermal path to ambient for inner stacked layers
• Conventional 2-mask approach for package fabrication, and either wire bonds or ClawConnect™ wafer-level interconnects from die to package
• Scalable to larger packages such as DRAM, or scalable to finer pitch
• Room-temperature bonding, requires no underfill, and is Pb (lead)-free

Product Roadmap

First-generation Design:

• Thin, stackable package that is less than 140-µm (micron) thick per layer
• Thickness of stack for 8 packaged chips is <1.2 mm— significantly less than competing 8-chip DRAM modules
• Uses standard wire bonding and flat solder-pad connection to board; ClawConnect™ springs are only used between packages

A single stackable package, with ClawConnect™springs providing interconnects to adjacent packages

Second-generation Design:

• Thin, stackable package that is less than 140 µm; target is <100 µm
• ClawConnect™ springs replace wire bonds, reducing cost and enabling even thinner packages
• Can be integrated with ClawConnect™ Wafer-Level Packaging to further reduce IC cost

Application Areas

• Memory and logic modules—high-density stacked packages for DRAM, SRAM (static random access memory), data device integration, Flash NOR/NAND gates, ASICs (application-specific integrated circuits)
• Stacked processors—improved thermal management
• Subsystems— heterogeneous chipsets
• Wireless, pocket PCs, and other mobile applications—higher density and maximum functional integration, with minimum footprint and low profile

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