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ClawConnect™ Wafer-Level Packaging, Burn-In, & Test

Today’s IC (integrated circuit) and device manufacturers are constantly struggling to reduce IC feature size and process costs, while still increasing product volume. Packaging and testing IC die as whole wafers prior to dicing is increasingly serving as a way to reduce handling and materials costs, as well as process times per die.

PARC’s ClawConnect™ technology is a powerful enabler for the broad implementation of WLP (wafer-level packaging), probing, burning-in, and testing of ICs. As a wafer-level technology, ClawConnect™ spring interconnects offer:
-   broad flexibility across multiple applications;
-   advantages in pitch and compliance;
-   Pb (lead)-free and solder-free contacts;
-   lower total cost of ownership.
Chip-on-board daisy chain

Solution Features

Compliant ClawConnect™interconnect replaces solder bumps
  • Elastically compliant interconnects replace plastically deforming solder bumps
  • Batch-fabricated, on-chip spring contacts act as z-compliant interconnects and probes for wafer-level testing and/or burn-in
  • High force of leveraged spring mechanics enables reliable solder-free pressure contacts
  • Spring interconnects are formed as the last metallization step, thus enabling a "free” redistribution layer as part of the spring-fabrication process
  • Low-cost spring fabrication uses conventional process tools and 3 or fewer masks
  • Assembly with standard SMT (surface mount technology) techniques can replace TSOP (thin small outline package), FBGA (fine-pitch ball grid array)
  • Compressible springs enable thinner packages, which are essential for portable devices
  • Probe cards and burn-in boards can be replaced by low-cost, low-maintenance flat contactors, since spring contacts are now on the wafer
  • Lateral scrubbing motion of springs on compression provides high contact quality

Application Areas

  • Mobile devices including cell phones, wireless handsets, and notebook PCs—portability and memory requirements are driving WLP adoption; cell phones consume more than 90% of WLP products today
  • Server memory/data storage—including DRAM (dynamic random access memory), SRAM (static random access memory), SDRAM (synchronous dynamic random access memory), DDRAM (double data rate-synchronous memory)—these high-volume applications require test and burn-in prior to end use
  • Other devices migrating to wafer level—including imaging and optoelectronic sensors, MEMS-based (micro-electro-mechanical systems) sensors, MOEMS-based (micro-optoelectronic mechanical systems) sensors, NEMS-based (nanoelectromechanical systems) sensors, digital cameras, wrist watches, flash memory, cell phone cameras, battery management, EPROMs (erasable programmable read-only memory), integrated passives, chip-on-board, RFID (radio frequency identification) tags, sockets, and chip carriers

Return to ClawConnect™ Spring Array Solutions

BUSINESS CONTACT
Nitin Parekh
Director of Business Development, Hardware Systems & Electronic Materials and Devices Laboratories
650-812-4132
RELATED WEBPAGES

StressedMetal™ MEMS Solutions

ClawConnect™ Spring Array Solutions

StressedMetal™ Fabrication and Assembly

NEWS AND PUBLICATIONS

Wafer Level Packaging Using StressedMetal® Technology, IMAPS Proceedings

Other Resources:

Evolution of Wafer-Level Packaging, Advanced Packaging

Emerging Packaging Technologies Offer Many Design Advantages for High-Speed Connections, Chip Scale Review

From Wafer Level Packaging to System Size Packaging (pp.18-19) [.pdf], SECAP Supplement

   

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