Design Rules and Prototype Examples for Additive Printing of Organic Complementary Circuits

Details

Event SPIE
San Diego, CA USA. Date of Talk: 8/10/2015

Speakers

Tse Nga Ng
Krusor, Brent S.
Kor, S.
Janos Veres
Event

Design Rules and Prototype Examples for Additive Printing of Organic Complementary Circuits

With the recent improvements in printed devices, it is now possible to build integrated circuit systems out of printed devices. The combination of sensor, logic, and rewritable memory will greatly enhance the functionalities of printed electronics. Non-volatile ferroelectric memory in passive or active matrix arrays has been demonstrated (Sekitani, et al., Science, 326 (2009) 15161519; Naber, et al., Adv. Mater., 22 (2010) 933945; Ng, et al., Org. Electron., 12 (2011) 20122018). The addition of addressing logic is necessary for these arrays to be scalable (Ng, et al., Sci Rep., doi:10.1038/srep00585): a binary logic decoder allows 2N rows in an array to be controlled with just N-bit lines. In addition to scaling memory arrays, the decoder logic is also widely applicable to arrayed sensor and display applications. At Palo Alto Research Center (PARC), we have demonstrated organic complementary circuits by inkjet printing. An example is a printed decoder for handling 3-bit address lines to an array of ferroelectric capacitors. In addition, another example is a temperature sensor tag, in which the control circuit is triggered to generate a pulse to write into the memory when the thermistor temperature exceeds a preset threshold. For these examples, simulation models are developed for the organic transistors to achieve circuit designs that tolerate the variations in printed devices, as well as to determine the minimum performance requirements for reliable digital logic circuits. I will discuss how we tackle the challenges of device variations and in printed transistors and the design rules we learned in the course of developing these circuits.

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