Integrating Through-Silicon Vias with Solder Free, Compliant Interconnects for Novel, Large Area Interposers

A novel packaging module is described that is based on co-integration of flexible micro-spring interconnects with through silicon copper vias (TSVs) onto a passive large area silicon interposer. We report on the test packaging vehicles based on such interposers that are designed to demonstrate a wafer scale integration process to form TSV+spring interconnects with high yield and low resistance. Our goal is to develop a scalable, large area die or MCM packaging platform to enable stress- free, readily reworkable packaging of chips and components with different functionality and technology. We show interposer layouts, share process details and characterization methods.