Scalable Microsprings for Integrated Test and Packaging

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Scalable Microsprings for Integrated Test and Packaging

We present microsprings to address key next generation flip chip packaging needs. The compliance enables test and re-work (reducing need for KGD), as the springs also serve as permanent contacts in the package. This can lower the cost of MCM and other packages. The springs also address thermal expansion mismatches to the substrate (large die chip to board demonstrated) for WLP chip-board applications. The stress isolation capabilities can also help fragile IC low-K and MEMS sensors. The springs are fabricated with wafer-scale processing, are lithographically defined and self assemble by rising off the surface. This enables very fine (6 um demonstrated) or large pitches (mms) and can achieve gap heights much smaller than solder (<20um demonstrated, 5um possible). We will review the motivations for using microsprings in packages and then describe multiple prototype demonstrations for various applications, including: high density optoelectronic, display drivers, memory wafer level packaging, and arrays of microprocessors. The daisy chain test chips for the processor applications were done with Oracle and demonstrate 180x180um pitch array, >2500 contacts, < 100mohm, and pass tests of >1000 thermocycles, > 1000 humidity hrs, and 250 mA.

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