Architecture Support for Parallel Programming

The key issue facing chip multiprocessors (CMPs) is the difficulty of writing parallel programs to run on them.

In this talk I will explain how support for thread-level speculation (TLS) in the memory system of a CMP can dramatically improve performance on sequential applications. I will briefly explain what TLS is and how it is implemented. I will also describe how TLS can be combined with managed-runtime languages such as Java to transparently convert sequential applications into parallel applications. I will also describe Transactional Coherence and Consistency (TCC). TCC is a way of exposing the benefits of TLS directly to the programmer using programmer defined transactions. TCC has the potential to simplify parallel programming by providing a smooth transition from sequential programs to parallel programs. I will briefly describe TCC and explain how to develop parallel applications using the TCC programming model.

Presenter(s)

Kunle Olukotun is an Associate Professor of Electrical Engineering and Computer Science. Olukotun has been a researcher in and proponent of CMP technology since the early 1990's. Olukotun led the Stanford Hydra single-chip multiprocessor research project which was the first microprocessor with multiple processors on a single silicon chip and support for thread-level speculation. Olukotun founded Afara Websystems to develop commercial server systems with significant performance/watt advantages using CMP technology. At Afara, Olukotun was chief scientist and the co-architect of the 8-core, 32-thread SPARC-based CMP. Afara was acquired by Sun Microsystems. The Afara microprocessor technology, now called Niagara (UltraSPARC T1), is at the core of Sun's "Throughput Computing" initiative. Olukotun is actively involved in research in computer architecture, parallel programming environments and scalable parallel system design. Olukotun received his Ph.D. from The University of Michigan.