The new paradigm of Multicore processors: Changing the focus from frequency to instructions per clock


Date Thursday March 9th 2006
Time 4:00-5:00pm
Venue George E. Pake Auditorium

PARC Forum

The computing industry has delivery years of continuous performance improvements, and computer usage models have changed dramatically as a result. The driving force behind this growth in performance was a dramatic boost in microprocessor frequency. Yet these frequency gains have now resulted in the microprocessors reaching practical power consumption limits. Innovation is leading the industry to the new paradigm of multicore processors, which change the focus from frequency, to instructions per clock. This new era will be discussed, as well as new usages it will enable.


Stephen S. Pawlowski is an Intel Senior Fellow. He is the Digital Enterprise Group chief technology officer and general manager for Architecture and Planning for Intel Corporation.

Pawlowski joined Intel in 1982. He led the design of the first Multibus I Single Board Computer based on the 386 processor. He was a lead architect and designer for Intel's early desktop PC and high performance server products and was the co-architect for Intel's first P6 based server chipsets. He helped define the system bus interfaces for Intel's P6 family processors, the Pentium® 4 processor and Itanium™ processor. He also created and led the research for Intel's agile radio architecture for a future generation of wireless products and prior to his current assignment was the director of Corporate Technology Group's Microprocessor Technology Lab.

Pawlowski graduated from the Oregon Institute of Technology in 1982 with bachelor's degrees in electrical engineering technology and computer systems engineering technology, and received a master's degree in computer science and engineering from the Oregon Graduate Institute in 1993.

Pawlowski holds 52 patents in the area of system, and microprocessor technologies. He has received three Intel Achievement Awards.

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