Current trends and progress in microelectronics continue to be enabled by chip packaging technologies. As die sizes, I/O counts, and power densities grow, significant challenges develop in connecting chips and their first-level packages. Additionally, ongoing interconnect evolutions in multi-chip module (MCM) packaging and 3D integration presents opportunities for novel I/O technologies that improve performance despite severe dimensional constraints. Electronic packaging based on stress-engineered spring interconnects  could potentially improve chip testing, rework, and mechanical compliance; and as I/O pad sizes and pitches reduce, these spring interconnects can be miniaturized to keep pace. The novel packaging has been demonstrated for circuits that were packaged onto substrates with integrated flexible microsprings. We report on the level one interconnects that are based on the array of compliant high density microsprings connecting the IC die to the ceramic or organic substrates. The microsprings replace the conventionally used solder reflown microbumps and present a stress free, lead free packaging solution. We report on the fabrication and performance of the stress engineered interconnects on the multi chip capable substrates. The substrates populated with microspring interconnects are a reusable MCM platform where ability to separate non-functional and functional (good) die is a key technology (KGD) enhancing assembly yield. We previously demonstrated a microspring that meets demanding electrical and mechanical requirements, with <100mohm per connection and >30m of compliance . These springs are lithographically defined metal cantilever beams with large initial stress gradients. When the springs are released from the substrate, the stress relaxes and their tips lift out of the substrate plane, becoming 3D compliant interconnects which can compress against a facing metal pad to form a contact. In the currently reported experiments fine pitch substrates with both ceramic and organic built-up layers have been populated with high density arrays of microsprings on the 180 um pitch. The substrates have been manufactured to house 14x16 mm2 test chips . The test chip is fabricated in 0.18 um CMOS technology and is specially designed for package characterization with its built-in metrology circuits. It consists of 3944 unit cells that can measure the connectivity and resistance of each individual spring connection. Each unit cell also has a programmable heater circuit that dissipates significant current to generate temperature gradients across the chip. This allows us to study the yield and reliability of the spring connections across temperature variations and under any resulting chip or package deformations. The test chip can rapidly switch between four different power profiles at 1 GHz to simulate dynamic work loads in a high-performance microprocessor. At full load, the test chip dissipates 355 W at 1.8 V. In this paper we report on The development of microfabrication process resulting in the integration of compliant high density microspring interconnects with the ceramic and organic IC substrates; Packages of the large footprint semiconductor die on the substrates with solder free interconnects, their configuration, assembly details, metrology and reliability experiments. Further applications of this packaging technology in the MCM environment are also discussed.
Shubin, I.; Chow, A.; Cunningham, J.; Giere, M.; Nettleton, N.; Simons, J.; Douglas, D.; Chow, E. M.; De Bruyker, D.; Cheng, B.; Anderson, G. B. A package demonstration with solder free compliant flexible interconnects. 60th Electronic Components and Technology Conference (ECTC); 2010 June 1-4; Las Vegas, NV., pp. 1429-1435