We are developing microsprings to address key next generation packaging needs. They provide compliance which enables basic pressure contact testing (gold-gold) and also permanent packaging. This integrated test and packaging capability addresses the known-good-die problem and changes the economics of building multi-chip modules. The springs also address differential thermal expansion mismatches to the substrates, and have demonstrated bare die silicon on organic substrates. As a sliding pressure contact, low K dielectric vulnerability is reduced. The flip chip gap height can be tuned to very small (5um) for compact applications or chip stacking, and can do high gaps (100s of um) to provide space for other components. The springs are fabricated with wafer-scale processing, are lithographically defined and self assemble by rising off the surface. This enables very fine pitches (6um demonstrated) or very large pitches (mms). After a quick review of our previous work in this area, this talk will focus on recent results targeting arrays of processors for Oracle. A spring contact was designed to achieve large compliance (>30um) and <100 mohm resistance. The test array has ~3000 contacts and is 180x180um pitch. Daisy chain test packages have been shown to pass over 1000 thermocyles and 1000 humidity hours. High current tests show stable resistances and <1deg temperature rise for 250 mA per contact. In addition to silicon substrates, the springs have been fabricated on organic and ceramic substrates. A custom IC designed to characterize the contacts was assembled, enabling resistance measurements of thousands of contacts. Characterization of the packages show resistances which match a solder based package. In addition to packaging, the fabrication technology has been used for a variety of MEMS devices includes high Q inductor coils (on active circuits), high angle mirrors, and AFM cantilevers and calorimeters.
Chow, E. M.; De Bruyker, D.; Cheng, B.; Shubin, I.; Chow, A. Microspring contacts for integrated test and packaging. International Wafer-Level Packaging Conference; 2010 October 11-14; Santa Clara, CA.